(preliminary) pl611s-18 0.5khz-125mhz mhz to khz programm able clock t m 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 2/23/07 page 1 features ? designed for very low-power applications ? offered in tiny green/rohs compliant packages o 6-pin dfn (2.0mmx1.3mmx0.6mm) o 6-pin sc70 (2.3mmx2.25mmx1.0mm) o 6-pin sot23 (3.0mmx3.0mmx1.35mm) ? accepts crystal or reference clock inputs ? input frequency: o fundamental crystal: 10mhz to 50mhz o reference input: 1mhz to 125mhz ? accepts >0.1v reference signal input voltage ? output frequency 0.5khz to 125mhz cmos. o 65mhz @ 1.8v operation o 90mhz @ 2.5v operation o 125mhz @ 3.3v operation ? one programmable i/o pin can be configured as oe, pdb, fsel or clk1 ? low current consumption: o <1.0ma with 27mhz & 32khz outputs o < 5ca when pdb is activated ? single 1.8v, 2.5v, or 3.3v 10% power supply ? operating temperature range from -40 c to 85 c description the pl611s-18 is a low-cost general purpose frequency synthesizer and a member of phaselinks picopll family, the worlds smallest programmable clocks. phaselinks pl611s-18 offers the versatilit y of using a single crystal (mhz) or reference clock input and producing up to two (khz/mhz) system clocks, or a combination of reference and low frequency outputs. the pl611s-18 is designed for low-power applications with very stringent space requirements and consumes ~1.0ma, while producing 2 distinct outputs of 27mhz and 32khz. the power down feature of pl611s-18, when activated, allows the ic to consume less than 5ca o f power. the pl611s-18 fits in a small dfn, sc70, or sot23 package. cascading of the pl611s-18 with other phaselink programmable clocks allow generating system level clocking requirements, thereby reducing the overall system implementation cost. in addition, one programmable i/o pin can be configured as output enable (oe), frequency switching (fsel), power down (pdb) input, or clk1 (clk0, f ref , f ref /2) output. block diagram phase detector charge pump loop filter vco xin/fin xout r-counter (5-bit) f vco = f ref * (2 * m/r) f out = f vco / (2 * p) clk f ref programming logic oe, pdb, fsel, clk1 xtal osc m-counter (8-bit) p-counter (14-bit) programmable cload programmable function
(preliminary) pl611s-18 0.5khz-125mhz mhz to khz programm able clock t m 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 2/23/07 page 2 key programming parameters clk output frequency output drive strength programmable input/output f out = f ref * m / (r * p) where m=8 bit r= 5 bit p= 14 bit clk0 = f out , f ref or f ref / (2*p) clk1 = f ref , f ref /2, clk0 or clk0/2 three optional drive strengths to choose from: ? low: 4ma ? std: 8ma (default) ? high: 16ma one output pin can be configured as: ? oe - input ? fsel - input ? pdb C input ? clk1 C output ? programmable cload package pin configuration and assignment pin assignment name dfn pin # sc70 pin# sot pin# type description xin, fin 1 3 3 i crystal or reference input pin. gnd 2 2 2 p gnd connection clk0 3 1 1 o programmable clock output vdd 4 6 6 p vdd connection oe, pdb, fsel, clk1 5 5 5 i/o this programmable i/o pin can be configured as an o utput enable (oe) input, power down input (pdb), frequenc y select input (fsel) or clk1 output. this pin has an inter nal 60kn pull up resistor on oe, pdb and fsel. state oe pdb fsel 0 tri-state clk power down mode bank 0 1 (default) operating mode operating mode bank 1 xout 6 4 4 o crystal output pin. do not connect if fin is used. 1 2 3 4 5 6 oe, pdb, fsel, clk1 gnd xin/fin clk0 xout vdd dfn dfn dfn dfn- -- -6 66 6l l l l ( (( (2 22 2. .. .0 00 0mmx mmx mmx mmx1 11 1. .. .3 33 3mmx mmx mmx mmx0 00 0. .. .6 66 6mm mmmm mm) )) ) sot sot sot sot23 2323 23- -- -6 66 6l l l l ( (( (3 33 3. .. .0 00 0mmx mmx mmx mmx3 33 3. .. .0 00 0mmx mmx mmx mmx1 11 1. .. .35 3535 35mm mmmm mm) )) ) 12 3 4 5 6 vdd clk0 xout sc scsc sc70 7070 70- -- -6 66 6l l l l ( (( (2 22 2. .. .3 33 3mmx mmx mmx mmx2 22 2. .. .25 2525 25mmx mmx mmx mmx1 11 1. .. .0 00 0mm mmmm mm) )) ) xin/fin oe, pdb, fsel, clk1 xin/fin clk0 xout gnd vdd oe,pdb,fsel,clk1 p p p p l l l l 6 6 6 6 1 1 1 1 1 1 1 1 s s s s - - - - 1 1 1 1 8 8 8 8 p p p p l l l l 6 6 6 6 1 1 1 1 1 1 1 1 s s s s - - - - 1 1 1 1 8 8 8 8 12 3 65 4 p p p p l l l l 6 6 6 6 1 1 1 1 1 1 1 1 s s s s - - - - 1 1 1 1 8 8 8 8 gnd
(preliminary) pl611s-18 0.5khz-125mhz mhz to khz programm able clock t m 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 2/23/07 page 3 functional description pl611s-18 is a highly featured, very flexible, adva nced programmable pll design for high performance, low- power, small form-factor applications. the pl611s- 18 accepts a crystal input of 10mhz to 50mhz or a r eference clock input of 1mhz to 125mhz and is capable of pro ducing two outputs up to 125mhz. this flexible des ign allows the pl611s-18 to deliver any pll generated frequenc y, f ref (crystal or ref clk) frequency or f ref /(2*p) to clk0 and/or clk1. some of the design features of the pl 611s-18 are mentioned below: pll programming the pll in the pl611s-18 is fully programmable. the pll is equipped with an 5-bit input frequency divider (r-counter), and an 8-bit vco frequency feedback loop divider (m-counter). the output of the pll is transferred to a 14-bit post vco divider (p-counter). the output frequency is determined by the following formula [f out = f ref * m / (r * p) ]. clock output (clk0) clk0 is the main clock output. the pl611s-18 can also be programmed to provide a second clock output, clk1, on the programmable i/o pin (see oe/pdb/fsel/clk1 pin description below). the output of clk0 can be configured as the pll output (f vco /(2*p)), f ref (ref clk frequency) output, or f ref /(2*p) output. the output drive level can be programmed to low drive (4ma), standard drive (8ma) or high drive (16ma). the maximum output frequency is 125mhz. clock output (clk1) the clk1 feature allows the pl611s-18 to have an additional clock output. this output can be programmed to one of the following: f ref f ref / 2 clk0 clk0 / 2 output enable (oe) the output enable feature allows the user to enable and disable the clock output(s) by toggling the oe pin. the oe pin incorporates a 60kn pull up resist or giving a default condition of logic 1. pulling t he oe pin low 0 will tri-state the output buffers. power-down control (pdb) the power down (pdb) feature allows the user to put the pl611s-18 into sleep mode. when activated (logic 0), pdb disables the pll, the oscillator circuitry, counters, and all other active circuitry and tri-state the output buffers. in power down mode t he ic consumes <5ca of power. the pdb pin incorporates a 60kn pull up resistor giving a defau lt condition of logic 1. frequency select (fsel) the frequency select (fsel) feature allows the pl611s-18 to switch between two pre-programmed outputs allowing the device on the fly frequency switching. the fsel pin incorporates a 60kn pull u p resistor giving a default condition of logic 1. programmable cload the pl611s-18 is equipped with programmable s- caps to allow the cload to be tuned from 8pf to 12pf.
(preliminary) pl611s-18 0.5khz-125mhz mhz to khz programm able clock t m 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 2/23/07 page 4 electrical specifications absolute maximum ratings parameters symbol min. max. units supply voltage range v dd - 0.5 7 v input voltage range v i - 0.5 v dd + 0.5 v output voltage range v o - 0.5 v dd + 0.5 v soldering temperature (green package) 260 c data retention @ 85 c 10 year storage temperature t s -65 150 c ambient operating temperature* -40 85 c exposure of the device under conditions beyond the limits specified by maximum ratings for extended pe riods may cause permanent damage to the device and affect product reliability. these conditions r epresent a stress rating only, and functional opera tions of the device at these or any other condition s above the operational limits noted in this specification is not implied. *operating temperature is guarante ed by design. parts are tested to commercial grade only. ac specifications parameters conditions min. typ. max. units crystal input frequency (xin) fundamental crystal 1 0 50 mhz @ v dd =3.3v 125 @ v dd =2.5v 90 input (fin) frequency @ v dd =1.8v 1 65 mhz input (fin) signal amplitude internally ac coupled (high frequency) 0.9 v dd vpp input (fin) signal amplitude internally ac coupled (low frequency) 3.3v < 50mhz, 2.5v < 40mhz, 1.8v < 15mhz 0.1 v dd v pp @ v dd =3.3v 125 mhz @ v dd =2.5v 90 mhz output frequency @ v dd =1.8v 65 mhz settling time at power-up (after v dd increases over 1.62v) 2 ms oe function; ta=25o c, 15pf load 10 ns output enable time pdb function; ta=25o c, 15pf load 2 ms vdd sensitivity frequency vs. v dd +/-10% -2 2 ppm output rise time 15pf load, 10/90% v dd , high drive, 3.3v 1.2 1.7 ns output fall time 15pf load, 90/10% v dd , high drive, 3.3v 1.2 1.7 ns duty cycle v dd /2 45 50 55 % period jitter,pk-to-pk* (measured from 10,000 samples) with capacitive decoupling between vdd and gnd. 70 ps * note: jitter performance depends on the programmi ng parameters.
(preliminary) pl611s-18 0.5khz-125mhz mhz to khz programm able clock t m 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 2/23/07 page 5 dc specifications parameters symbol conditions min. typ. max. units supply current, dynamic, with loaded cmos outputs i dd @ v dd =3.3v, 27mhz, load=15pf 4.0 ma supply current, dynamic, with loaded cmos outputs i dd @ v dd =2.5v, 27mhz, load=10pf 2.7 ma supply current, dynamic with loaded cmos outputs i dd @ v dd =1.8v, 27mhz, load=5pf 0.9 ma pll off: supply current, dynamic, with loaded cmos output i dd @ v dd =3.3v, 27mhz, load=15pf 2.0 ma pll off: supply current, dynamic, with loaded cmos output i dd @ v dd =2.5v, 27mhz, load=10pf 1.3 ma pll off: supply current, dynamic with loaded cmos output i dd @ v dd =1.8v, 27mhz, load=5pf 0.8 ma pll off: supply current, dynamic with loaded cmos output i dd @ v dd =1.8v, 32khz, load=5pf 0.2 ma supply current, dynamic, with loaded outputs i dd when pdb=0 5 ca operating voltage v dd 1.62 3.63 v output low voltage v ol i ol = +4ma standard drive 0.4 v output high voltage v oh i oh = -4ma standard drive v dd C 0.4 v output current, low drive i osd v ol = 0.4v, v oh = 2.4v 4 ma output current, standard drive i osd v ol = 0.4v, v oh = 2.4v 8 ma output current, high drive i ohd v ol = 0.4v, v oh = 2.4v 16 ma short-circuit current i s 50 ma * note: please contact phaselink, if super-low-powe r is required. crystal specifications parameters symbol min. typ. max. units fundamental crystal resonator frequency f xin 10 50 mhz crystal loading rating (the ic can be programmed for any value in this ran ge.) c l (xtal) 8 12 pf maximum sustainable drive level 100 w operating drive level 30 w shunt capacitance c0 5.5 pf metal can crystal esr max esr 50 n shunt capacitance c0 2.5 pf small smd crystal esr max esr 80 n
(preliminary) pl611s-18 0.5khz-125mhz mhz to khz programm able clock t m 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 2/23/07 page 6 pcb layout considerations for performance optimizat ion dfn-6l evaluation board the following guidelines are to assist you with a p erformance optimized pcb design: signal integrity and termination considerations - keep traces short! - trace = inductor. with a capacitive load this equ als ringing! - long trace = transmission line. without proper termination this will cause reflections ( looks lik e ringing ). - design long traces as striplines or microstrip s with defined impedance. - match trace at one side to avoid reflections boun cing back and forth. decoupling and power supply considerations - place decoupling capacitors as close as possible to the vdd pin(s) to limit noise from the power supply - multiple vdd pins should be decoupled separately for best performance. - addition of a ferrite bead in series with vdd can help prevent noise from other board sources - value of decoupling capacitor is frequency depend ant. typical values to use are 0.1 f for designs using crystals < 50mhz and 0.01 f for designs using crystals > 50mhz. typical cmos termination place series resistor as close as possible to cmos output cmos output buffer ( typical buffer impedance 20 ) to cmos input series resistor use value to match output buffer impedance to 50 trace. typical value 30 50 line
(preliminary) pl611s-18 0.5khz-125mhz mhz to khz programm able clock t m 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 2/23/07 page 7 crystal tuning circuit series and parallel capacitors used to fine tune t he crystal load to the circuit load . cst ? series capacitor, used to lower circuit load to m atch crystal load . raises frequency offset. this can be eliminated by using a crystal w ith a cload of equal or greater value than the oscillator. cpt ? parallel capacitors , used to raise the circuit lo ad to match the crystal load. lowers frequency offset . crystal xin 1 8 xout cpt cpt cst
(preliminary) pl611s-18 0.5khz-125mhz mhz to khz programm able clock t m 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 2/23/07 page 8 d e pin1 dot d1 b e e1 l a3 a a1 pin 6 id chamfer package drawings ( green package compliant) sot23-6l sc70-6l dfn-6l dimension in mm symbol min. max. a 1.05 1.35 a1 0.05 0.15 a2 1.00 1.20 b 0.30 0.50 c 0.08 0.20 d 2.80 3.00 e 1.50 1.70 h 2.60 3.0 l 0.35 0.55 e 0.95 bsc dimension in mm symbol min. max. a 0.80 1.00 a1 0.00 0.09 a2 0.80 0.91 b 0.15 0.30 c 0.08 0.25 d 1.85 2.25 e 1.15 1.35 h 2.00 2.30 l 0.21 0.41 e 0.65bsc dimension in mm symbol min. max. a 0.50 0.60 a1 0.00 0.05 a3 0.152 0.152 b 0.15 0.25 e 0.40bsc d 1.25 1.35 e 1.95 2.05 d1 0.75 0.85 e1 0.95 1.05 l 0.20 0.30 c l a2 e h d a1 e b a pin1 dot c l a2 e h d a1 e b a pin1 dot
(preliminary) pl611s-18 0.5khz-125mhz mhz to khz programm able clock t m 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 2/23/07 page 9 ordering information ( green package) for part ordering, please contact our sales departm ent: 47745 fremont blvd., fremont, ca 94538, usa tel: (510) 492-0990 fax: (510) 492-0991 part number the order number for this device is a combination of the following: part number, package type and operating temperature range pl611 s-18-xxx x x x part /order number marking ? package option pl611s-18-xxxgc-r xxx 6-pin dfn (tape and reel) pl611s-18-xxxuc-r xxx 6-pin sc70 (tape and reel) pl611s-18-xxxtc-r 18xxx 6-pin sot23 (tape and reel) ? note: xxx designates marking identifier that, at times, could be independent of the part number. pl ease consult your phaselink sales f or marking information. phaselink corporation, reserves the right to make c hanges in its products or specifications, or both a t any time without notice. the information furnished by phaselink is believed to be accurate a nd reliable. however, phaselink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any lo ss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : phaselinks products are not authorized for use a s critical components in life support devices or sy stems without the express written approval of the president of phasel ink corporation. solder reflow profile available at www.phaselink.com/qa/solderinggreen.pdf part number temperature c=commercial i = industrial package type g=dfn-6l u=sc70-6l t=sot - 6l 3 digit id code * (will be assigned at programming time) n one= tube r=tape and reel
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